1. Field of the Invention
The invention relates to integrated circuit devices and more particularly to layout techniques for such devices.
2. Description of Related Art
One area where parasitic capacitance is noted is in input/output (I/O) buffer circuits. For high speed I/O circuits, the parasitic capacitance is one limiter to the fast transitioning edges of the circuit. The larger the capacitance, the slower the charging or discharging, resulting in degraded bus performance. Thus, many efforts have been put forth to reduce the capacitive load and create faster transitions which in turn leads to faster I/O circuits.
The input signals to an integrated circuit, for example, a metal oxide semiconductor (MOS) integrated circuit, are generally fed to transistors. If the voltage applied to the transistor becomes excessive, the gate oxide can break down, the junctions can be destroyed, and the metal to the transistor can be destroyed. Excessive voltages are voltages in excess of the normal operating voltages of the circuit. For example, voltages far in excess of the nominal operating voltage of an integrated circuit, may be impressed upon the inputs to the circuit during either human-operator or mechanical handling operations.
The main source of excessive high voltages to integrated circuits is triboelectricity. Triboelectricity is caused when two materials are rubbed together. A common situation is a person developing very high static voltage (i.e., a few hundred to a few thousand volts) simply by walking across a room or by removing an integrated circuit from its plastic package, even when careful handling procedures are followed. If such a high voltage is applied to the pins of an integrated circuit package, its discharge, referred to as ElectroStatic Discharge (ESD), can cause breakdown of the devices to which the voltage is applied. The breakdown event may cause sufficient damage to produce immediate destruction of the integrated circuit, or it may weaken the device enough that it will fail early in the operating life of the integrated circuit.
In general, all inputs (e.g., pins) of MOS integrated circuits are provided with protection circuits to prevent excessive voltages from damaging the MOS transistors. These protection circuits are normally placed at the input and output pads on a chip and the transistor gates to which the pads are connected. The protection circuits are designed to begin conducting or to undergo breakdown, thereby providing an electrical path to ground (or to the power-supply rail), in the presence of excessive voltages, generally ESD. Since the breakdown mechanism is designed to be non-destructive, the circuits provide a normally open path that closes only when a high voltage appears at the input or output terminals, harmlessly discharging the node to which it is connected.
Typically, two types of protection circuits are used to provide protection against ESD damage: Diode breakdown and diode conduction. Diode protection is obtained by using the diode-breakdown or diode-conduction phenomenon to provide an electrical path in the semiconductor, e.g., silicon, substrate that consists of a diffused diode region of a doping type opposite to that of the substrate (for example, p-type and n-type doping, respectively). This diffused region is connected between the input pad and substrate. If a reverse-bias voltage greater than the breakdown voltage of the resultant pn junction is applied, the diffusion region (which otherwise works as a diode) undergoes breakdown. Furthermore, the diffused region will also clamp a negative-going ESD transition at the chip input to one diode drop below the substrate voltage. In CMOS technologies, an additional protection diode can be added by utilizing the pn junction that exists between a p-type region and the body region of the PMOS device (an n-type region that is connected to V.sub.CC). This diode is utilized as a protection device when a connection is made between the pad and a p-type region. This diode will generally clamp positive-going transitions to one diode drop above V.sub.CC (V.sub.CC is generally OV during ESD).
FIG. 1 shows a known input/output (I/O) buffer circuit 10 having ESD protection components, diodes D1 and D2. CMOS I/O buffer circuit 10 includes PMOS device 20 coupled to NMOS devices 30. The devices of circuit 10 are connected to I/O pad 40. Between pad 40 and the devices is a negative zap protection diode D1. Between I/O pad 40 and PMOS circuit 20 is forward-biased protection diode D2.
FIG. 2 shows a prior art layout of a portion of I/O buffer circuit 10 of FIG. 1, specifically illustrating the layout of PMOS device 20 and ESD protection diode D2. FIG. 2 shows PMOS field effect transistor (MOSFET) device 20 made up of polysilicon gate 60 separating source region 65 and drain region 70 with individual contacts 72 and 75 to source and drain regions 65 and 70, respectively. In this embodiment, PMOS device 20 is in an n-well with p-type (p.sup.+ doped) source and drain regions 65 and 70, respectively. FIG. 2 also shows conventional PMOS diode D2 adjacent drain 70 of PMOS device 20. In FIG. 2, p-type area 70 acts as both a MOSFET drain 70 and the D2 diode anode. Adjacent drain/anode 70 is an n-type (n.sup.+ -doped) cathode region 80 in the n-well.
The critical size of a protection circuit and of a performance circuit are independent of one another. For example, protection diodes D1 and D2 are sized (i.e., a specific volume of semiconductor material allocated) in accordance with the amount of charge that is contemplated to be dissipated. If the power is dissipated into too small a volume of silicon, the silicon can be heated beyond its melting point and the device destroyed. Transistor devices 20 and 30 are likewise sized, for example, in accordance with the voltage drive capabilities of the output driver.
In typical prior art structures, such as the I/O scheme illustrated in FIGS. 1 and 2, the size of PMOS protection D2 diode corresponds to the size of the PMOS device because they share a common junction (drain or anode). To accommodate layout concerns and processing conveniences, D2 diode is integrated with PMOS device 20. In other words, the critical size of either D2 diode or PMOS device 20 determines the size of the corresponding device. If D2 diode size is critical and controls, PMOS device 20 size is enlarged to accommodate the large diode. If, on the other hand, PMOS device 20 is critical and controls, D2 diode size is enlarged beyond what is necessary for an ESD protection circuit. It is to be appreciated that techniques for determining a critical diode size for addressing ESD concerns are well known and, so as not to obscure the invention, will not be discussed herein. For purposes of the invention, it is necessary to understand only that there is a critical, scaleable minimum size, for example, a minimum sized D2 diode, that will protect a performance circuit, such as a PMOS device or NMOS device, from ESD damage. Similarly, it is well known in the art how to size performance circuits, such as PMOS drivers. Accordingly, techniques for sizing performance circuits will not be presented herein.
I/O circuit 10 pad capacitance has several elements, including the NMOS device, the PMOS device, the wire bond or C4 pad, the pad to V.sub.CCP diode (D2) and the V.sub.SS to pad diode (D1). The diffusion capacitance is high because it is a p.sup.+ -type diffusion in an n-type well. As noted above, the typical PMOS device 20 of an I/O circuit includes a D2 diode, where one edge of the p-type drain serves as the drain and the other as the diode anode or edge. This sharing makes the diode scale up or down with PMOS device 20 size. For example, in a mixed voltage environment, when a high voltage technology wants to drive a low voltage I/O, PMOS device 20 size can be very large. Therefore, D2 diode size is much larger than required resulting in extra capacitive loading.
On the other hand, there are also performance circuits that do not need a large PMOS pull-up device. One example is an open drain buffer. To meet the minimum diode size requirement, however, the PMOS size is increased (and generally tied off).
Increasing the size of either the MOSFET device or the ESD protection circuit, e.g., diode, directly leads to increased capacitance. In general, the size of a device (e.g., area, volume, etc.) is directly related to its parasitic capacitance. Thus, what is needed is a layout, particularly an I/O layout, that minimizes parasitic capacitance contributed by the performance and protection circuits without sacrificing the required actions of either circuit.